(1) Field of the Invention
The present invention relates to a semiconductor memory device having memory cells divided into a plurality of separated blocks, and more particularly, to a semiconductor memory device having a test circuit enabling a simultaneous test for the plurality of blocks.
(2) Description of the Related Art
In recent years, dynamic metal-oxide semiconductor (MOS) random access memories (RAM's) have been enlarged to 1 Mbit. However, as the integration density of devices has increased, the test time period for such devices has also increased. Particularly, in a RAM having a small number of output bits, the test time period thereof is remarkably increased.
On the other hand, as the integration density has become higher, the number of memory cells connected to one sense amplifier for the read operation has become higher and, accordingly, the load of each sense amplifier has also become higher so as to reduce the speed of the read operation. In order to reduce the load of each sense amplifier, two or more series of sense amplifiers are provided. That is, the memory cells, sense amplifiers, row address decoders, and the like are divided into two or more blocks.